William D Clinger <email@example.com> wrote:
| Frode Vatvedt Fjeld wrote:
| > http://en.wikipedia.org/wiki/Sequential_consistency).
| Few modern multiprocessors guarantee sequential consistency as
| defined by that Wikipedia article. In general, the processor that
| issues a store instruction may see the result of that store before
| other processors.
That's not incompatible with "sequential consistency", which only
requires that there exist *some* potential global sequential order
of execution that matches what each processor sees. Or said another
way, your notion of "before" is too strict, implying absolute time
[which is not necessary for sequential consistency].
Cc-NUMA systems such as SGI's "Origin" and "Altix" *do* provide
sequential consistency in the usual interpretation of Leslie
Lamport's term, to which the Wikipedia article refers.
[Historical note: While "Origin" was initially designed to be able
to support "release consistency" as an option, it was found that
too many existing customer codes assumed sequential consistency,
so AFAIK release consistency was never enabled in shipped product
(and was perhaps never even fully debugged).]
| If you want sequential consistency in a multiprocessor system,
| with most current hardware, you need to follow certain rules when
| writing your program, and you need a compiler that inserts memory
| barriers according to certain rules, and also limits its optimizations
| to conform to certain rules.
If that is necessary, then I would say that such a multiprocessor
system does *not* provide sequential consistency in the hardware.
SGI's "Origin" and "Altix" do (and presumably a number of other
non-x86 platforms as well).
Rob Warnock <firstname.lastname@example.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607