Subject: Re: Implementing multithreading in Lisp
From: (Rob Warnock)
Date: Fri, 21 Nov 2003 07:15:29 -0600
Newsgroups: comp.lang.lisp
Message-ID: <>
Tim Bradshaw  <> wrote:
| * Alan Shutko wrote:
| > You can only have shared memory up to a pretty small number of CPUs,
| > 16 or so. 
| Bullshit.  Large commercial machines are essentially all
| cache-coherent shared memory systems, and large systems are 70-100
| CPUs.  Yes, of course, they're doing a lot of clever HW and SW tricks
| to do this, and they may or may not actually share one large memory
| system (SGIs don't I think, E10ks did, Sunfires probably don't, don't
| know about the big HP and IBM boxes), but they look like shared memory
| to applications.

SGI Origin systems *do* cache-coherently share one large memory address
space, even though that "single system image" (SSI) is actually made up
of smaller memories scattered throughput the nodes of the ccNUMA system.
That single image obeys the same "sequential consistency"[1] cache-coherency
model which user programs see on classic snoopy-cache bus SMP systems.
Standard Origin systems can have up to 512 CPUs per SSI (though up to
1024 have been shipped in to a few special customers), with up to 1 TB
of cache-coherent main memory.


[1] Some versions of the hardware were capable of being run with the
    looser "release consistency" model, but the improvement in performance
    on the small number of applications for which it would theoretically
    make a significant difference was never felt to be worth the trouble
    of fixing the operating system and all of the standard utilities to
    handle it, so Origin (MIPS/Irix) has always shipped with "sequential

Rob Warnock			<>
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