Tim Bradshaw <tfb+google@tfeb.org> wrote:
+---------------
| It's not really safe to generalise from a single instance, of course.
| Clearly as the number of cores go up various tradeoffs have to be
| made.  Of course, one thing that I don't think Rob mentioned is that
| one thing you can do, *if* you have enough pllism to exploit, is to
| have a large number of cores each clocked relatively slowly.  Power
| goes as some quite nasty power of clock speed (2? 4?), so you win
| this way.
+---------------

Actually, my point was that as transistor geometries get ever smaller,
the leakage current has become a serious source of power dissipation
even when running at *zero* clock speed -- and will continue to grow
even worse, unless something changes drastically[1], and become a
larger & larger percentage of the total power budget. [Some claim
it's *already* as much as 50% of the power!]


-Rob

[1] I'm not sure the recent announcements by Intel & IBM on "high-K"
    dialectrics counts as a "drastic" change, though it certainly has
    the possibility to push back the "leakage wall" a little bit longer.

    http://www.computerworld.com/blogs/node/4462
    http://arstechnica.com/news.ars/post/20070127-8716.html
    http://www.betanews.com/article/IBM_Also_Reinvents_the_Transistor/1170200107
    http://www.playfuls.com/news_05981_IBM_AMD_and_Intel_Fight_for_Supremacy_in_45nm_Chip_Technology.html

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Rob Warnock			<rpw3@rpw3.org>
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