Petter Gustad  <newsmailcomp4@gustad.com> wrote:
+---------------
| Jouni Matti Juhani Osmala <josmala@nimaatre.hut.fi> writes:
| > Petter Gustad <newsmailcomp4@gustad.com> writes:
| > > Ole Myren Rohne <ole.rohne@fys.uio.no> writes:
| > > > Marco Antoniotti <marcoxa@cs.nyu.edu> writes:
| > > > > Once you have chosen your Hardware Design Language (VHDL, Verilog...
| > > > That's cheating! He needs to start defining a lisp-based HDL;-)
| > > Well, you could write it in EDIF, which is Lisp :-)
| > Well, I personally like lisp, and dislike VHDL, can EDIF be recommended
| > as a general purpose HDL?
| 
| No (notice the smiley). EDIF is a netlist format. However, you could
| probably write some clever macros and functions in order to produce
| some readable and maintainable HDL descriptions in Common Lisp if you
| had an EDIF simulator (or you could convert the EDIF to verilog prior
| to simulation).
+---------------

Here's one design/simulation approach, albeit somewhat dated by now:

	<URL:http://www.swiss.ai.mit.edu/~jaffer/SIMSYNCH>
	<URL:http://www.swiss.ai.mit.edu/~jaffer/Work/scm95-1>
	<URL:http://www.swiss.ai.mit.edu/~jaffer/Work/scm97>


-Rob

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Rob Warnock, PP-ASEL-IA		<rpw3@rpw3.org>
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